Akshay Bhat
Design Verification Engineer
Munich
Summary
Experienced Semiconductors professional with over 6 years of experience in SOC design and Verification. Excellent reputation for resolving problems and improving overall SOC quality. Right now, seeking full time position as a Safety architect which offers professional challenges, new learning opportunities building up on current skills and knowledge.
Overview
7
7
years of professional experience
8
8
years of post-secondary education
Work History
Design Verification Engineer
NXP semiconductors
Munich
08.2017 - Current
- Good understanding of definition, planning, and execution of verification activities - over 5 years' experience in NXP products namely S32S200, AE270, S32S250, IMX95 family
- Experience in Testbench architecture development and verification with standard verification frameworks like UVM, OVM, C and System Verilog
- Good know-how in use of EDA tools for development, simulation and debug of functional tests
- Experience in NXP SOC architecture, verification process and expertise in verification of Safety modules
Design Verification Engineer
Infineon Technologies AG, Fa.Chipglobe GmbH
Munich
01.2016 - 03.2017
- RTL verification of automotive body power products - RADAR applications
- Experience in Verification flow from Testbench architecture development to Tape-out
- Experience in developing complex testcases using 'Constrained Random Stimulus Generation' as well as directed test sequences
- Experience in implementation of TB architecture for MMIC-AURIX co-verification
Education
Master of Science - Electronics Engineering, Microsystems
Hochschule Bremen
Bremen, Germany 04.2014 - 01.2016
Bachelor of Engineering - Electronics And Telecommunication
Visvesvaraya Technological University
06.2007 - 05.2010
Diploma in Electronics And Communication -
Department of Technical Education (D.T.E)
Bengaluru, India 06.2004 - 05.2007
Skills
Levels: German: A1/A2: Basic user English: Proficient
undefinedAccomplishments
- Innovative and efficient implementation of metric driven mixed signal verification testbench as a part of Master thesis
- Involved in definition, implementation and Tapeout of high value projects throughout the career
- Proactive approach in completing number of NXP projects - S32S200 , AE270, S32S250, IMX95 family
- Grown in verification roles from handling smaller modules to independently executing Safety verification in IMX95
Timeline
Design Verification Engineer
NXP semiconductors
08.2017 - Current
Design Verification Engineer
Infineon Technologies AG, Fa.Chipglobe GmbH
01.2016 - 03.2017
Master of Science - Electronics Engineering, Microsystems
Hochschule Bremen
04.2014 - 01.2016
Bachelor of Engineering - Electronics And Telecommunication
Visvesvaraya Technological University
06.2007 - 05.2010
Diploma in Electronics And Communication -
Department of Technical Education (D.T.E)
06.2004 - 05.2007
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