Anto Maria Jesudoss
Coimbatore
Summary
SOC/ASIC Physical Implementation and Design Engineer with 8 years of hands-on expertise by working in range of projects from Mobile Chips, Server IC and Sensors in lower node Technologies. Enthusiastic to learn and open to new challenges.
Overview
9
9
years of professional experience
Work History
Development Engineer
ELMOS Semiconductor
08.2023 - Current
Lead Engineer
Cadence Design Systems
10.2022 - 04.2023
- Leading team of 3 in the Digital Implementation of Place and Route with Analog on Top (40nm Technology).
- Setting up the flow, preparation of cds.lib, resolved the floorplan challenges in a rectilinear shape core area built based on Top Analog module resulting in routing congestion due to notchy edges, DRC issues and SDC clean up.
Staff Engineer
Samsung Semiconductor India Research
10.2018 - 05.2022
- Have worked in multiple tape outs (10nm and 5nm) being responsible for Synthesis, Timing Closure, STA and SignOff checks such as Equivalence check, Conformal Low Power and Logical DRC .
- Worked on the floor-plan with notchy edges, taking precautionary measures such as addition of partial blockages to avoid congestion due to buffer addition for hold fixes.
- Worked on partitions were setup timing become very critical, so logic were placed closer to each other.
- Worked on multi-voltage blocks where timing closure on the feedthrough signals were challenging and secondary power routing has to be managed during ECO stage.
Engineer
Altran Technologies India Private Limited
12.2017 - 10.2018
- Responsible for checking the quality of the design files, IO constraints, UPF, mapped and unmapped ports through Formal Verification.
Physical Design Engineer I
Mirafra Technologies
08.2015 - 11.2017
- Performed Physical Verification checks and fixes
Education
Master of Science - Microelectronics and Microsystems
Technical University Hamburg Harburg
2014
B.Tech - Electronics and Communication Engineering
Sri Ramakrishna College of Engineering
2011
Skills
RTL2GDSII
- Synthesis
- Place and Route (PnR) - Innovus, ICC2
- STA (PrimeTime), ECO's & Low Power checks (VCLP)
- Formal Verification (Equivalence Check)
- Physical Verification (Calibre)
Team Management
Experience in EDA tools of Cadence and Synopsys
Languages
German
Intermediate
B1
English
Bilingual or Proficient (C2)
Tamil
Bilingual or Proficient (C2)
English
Bilingual or Proficient (C2)
Tamil
Bilingual or Proficient (C2)
English
Bilingual or Proficient (C2)
Tamil
Bilingual or Proficient (C2)
Timeline
Development Engineer
ELMOS Semiconductor
08.2023 - Current
Lead Engineer
Cadence Design Systems
10.2022 - 04.2023
Staff Engineer
Samsung Semiconductor India Research
10.2018 - 05.2022
Engineer
Altran Technologies India Private Limited
12.2017 - 10.2018
Physical Design Engineer I
Mirafra Technologies
08.2015 - 11.2017
Master of Science - Microelectronics and Microsystems
Technical University Hamburg Harburg
B.Tech - Electronics and Communication Engineering
Sri Ramakrishna College of Engineering
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