Arinnita Chutia
HARDWARE DESIGN ENGINEER
Neubiberg
Summary
5+ years of experienced in RTL design using Verilog/VHDL, performed CDC, LINT and DFT checks on modules, additional checks using JasperGold, familiar with the safety analysis concept (FMEA, FMES, Fault Tree Analysis), working closely with the verification and backend team.
Overview
12
12
years of professional experience
7
7
years of post-secondary education
4
4
Languages
Work History
Design Engineer
Socionext Europe GmbH
10.2019 - Current
- RTL designing for modules and IPs (e.g Display Stream Compression Decoder test module, Idhash bypass, remote handler) using Verilog language, prepared Testcases for simulation.
- Spyglass checks (lint, CDC and Dft) and implementation (e.g. .sdc, Makefile etc).
- JasperGold checks for all the designs (e.g. super lint and xprop).
- Working closely with the verification and the backend team.
- Running simulation (using ModelSim and VCS) for 3rd party IPs.
- Hands on experience on multiple ASIC projects and prepared specification documentation for the modules.
- Documenting and preparing roadmap on confluence.
- Carried out validation for modules and IPs.
- Getting familiar with LEC (Logic Equivalence Check) for future projects.
Embedded Hardware Developer
Ferchau Engineering GmbH
03.2019 - 07.2019
- Using VHDL code for image processing on Spartan6.
- Created a testing environment.
- Developed linearity pattern to check the quality of the camera, identified reason for image lag.
- Built programming cable and test boards (in the lab).
- Documented specification and procedure to carry out specific tasks.
Master Thesis Student
CODESYS GmbH
02.2018 - 07.2018
- Thesis- Support on multicore CPUs in Embedded Systems.
- Using C language on microcontroller TC299TF developed Runtime System for CODESYS software.
- Initialised all the cores of the microcontroller, the hardware timer and router.
- Found the best method to achieve a synchronisation between all the cores of the microcontroller.
- Came up with the best protocol for interface which is Remote Procedure Call(RPC).
- Successfully implemented synchronisation and interface protocol between multicore processors.
- Resulted in more safe environment for several application to run on mobile machines when interfaced with CODESYS software.
Intern
Rohde & Schwarz GmbH
04.2017 - 06.2017
- Development of Protocol Analyzer with ZYNQ SoC.
- Evaluated the use cases for the analyzer.
- Created an interface description.
- Also implemented a FPGA module using VHDL language.
- Generated a FPGA module out of a system generator model.
- Prepared documentation and Graphical designs.
- Resulted in better performance Analyzer which will be used for future devices.
Transaction Risk Investigator
AMAZON DEVELOPMENT CENTER INDIA PVT. LTD.
09.2013 - 03.2016
- Experienced in e-commerce primarily in detecting online frauds and stolen credit cards.
- Successfully implemented ideas and logic to make amazon most safest and trusted place to transact online for both buyers and Sellers.
- Managed potential risks from third party sellers in global.
- Enforced policies on third party sellers to maintain online transaction fortified.
- Direct impact decision making - affecting both the financial as well as credibility facets of the organisation.
Education
Master Of Science - Electronics
Hochschule Bremerhaven
04.2016 - 12.2018
Bachelor Of Technology - Instrumentation
SRM University
08.2009 - 06.2013
Skills
Assembly language
C
SystemVerilog
Verilog
VHDL
Eclipse IDE
GIT
GNU
Hightec IDE
JasperGold
undefinedWebsites
Hobbies
Running, traveling, hiking, dancing
Timeline
Design Engineer
Socionext Europe GmbH
10.2019 - Current
Embedded Hardware Developer
Ferchau Engineering GmbH
03.2019 - 07.2019
Master Thesis Student
CODESYS GmbH
02.2018 - 07.2018
Intern
Rohde & Schwarz GmbH
04.2017 - 06.2017
Master Of Science - Electronics
Hochschule Bremerhaven
04.2016 - 12.2018
Transaction Risk Investigator
AMAZON DEVELOPMENT CENTER INDIA PVT. LTD.
09.2013 - 03.2016
Bachelor Of Technology - Instrumentation
SRM University
08.2009 - 06.2013
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