6+ years of hands-on experience in DFT methodologies, ATPG, simulations, and silicon bring-up.
Proficient in scan insertion , test pattern generation , and coverage analysis .
Collaborative team player with a passion for optimizing test strategies.
Automotive Chip DFT :
o Proficient in DFT methodologies for automotive chips.
o Worked on cluster-level and top-level scan insertion, ATPG, and simulations.
Fault Models Expertise :
o Extensive experience with various fault models, including stuck-at, transition, IDDQ, cell-aware, and UDFM.
LBIST (Logic Built-In Self-Test) :
o Skilled in LBIST techniques.
Coverage Analysis :
o Analyzed test coverage for stuck-at, transition, and LBIST.
o Work along with IP teams for coverage analysis and give feedback.
Retargeting and Simulations :
o Proficient in retargeting and conducting top-level simulations.
o Debugged issues during simulations.
SpyGlass DFT :
o Utilized SpyGlass for RTL cleanup in DFT flows.
Silicon Diagnosis and Bring-Up :
o Experience in silicon bring-up activities and post-silicon support.
Scan Insertion:
o Worked on scan insertion at the cluster level.
o Conducted DRC analysis during scan insertion and provided feedback to the design team for RTL updates.
ATPG :
o Set up ATPG and simulation environments for stuck-at and transition tests.
o Achieved detailed coverage analysis, with 99% stuck-at and 90% transition coverage.
Retargeting and Simulations:
o Performed retargeting and executed top-level Extest ATPG and simulations.
Verification:
o TAP network integration and verification for the SOC.
Silicon Bring-Up and Support:
o Contributed to silicon bring-up activities.
o Provided comprehensive support throughout the silicon lifecycle.
DFT Tools:
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