Ehtsham Ul Hassan
Munich
Summary
Dynamic Design Verification Engineer with a proven track record at Texas Instruments and RapidSilicon, excelling in UVM methodologies and mixed-signal design. Adept at enhancing verification processes and achieving coverage targets, while fostering cross-functional collaboration. Skilled in digital and mixed-signal verification and recognized for strong teamwork and communication abilities. Passionate about delivering high-quality semiconductor solutions.
Overview
6
6
years of professional experience
Work History
Master Thesis Student
Texas Instruments
Freising
04.2025 - 09.2025
- Verification of a multi-chip mixed signal system with a precision DS-ADC and disturbance-resistant communication channel using UVM methodology and advanced AMS/HDL modeling techniques
- Created digital model of a CDR circuit for clock and data recovery in a TX-RX communication channel
- Designed the schematic of the CDR circuit in Cadence Virtuoso and performed AMS simulations to validate mixed-signal functionality
- Developed mixed-signal Verilog-AMS transmitter & receiver models with cross-connection support, power supplies, and bias current checkers, and performed AMS simulations using a directed Verilog-AMS testbench
- Developed a mixed-signal Verilog-AMS testbench for a clock multiplier PLL based on system specifications to ensure stability, and verified functionality through directed AMS simulations
- Ported the Verilog-AMS testbench to Virtuoso and replaced the PLL loop filter with its schematic design to correlate simulation results between the Verilog-AMS model and schematic components.
Digital Design Engineering Working Student
Texas Instruments
Freising
10.2024 - 03.2025
- Provided digital verification support to Tucson, AZ design team for a 24-bit ADC, enhancing UVM testbench functionality and developing targeted test cases with emphasis on I2C interface protocol
- Owned the setup, development, and continuous improvement of the UVM-MS testbench for digital and DMS/AMS verification of an isolated ADC with integrated power
1. Developed and refined SystemVerilog assertions (SVA) to improve design verification
2. Designed and implemented frequency checkers to ensure signal integrity and performance
3. Created and maintained UVM register abstraction layer (UVM RAL) and pin agent(s) to streamline verification process
4. Developed comprehensive test cases to validate functional and interface requirements across multiple ADC designs
Digital Design Engineering Intern
Texas Instruments
Freising
05.2024 - 10.2024
- Exploring and leveraging of UVM-MS for Isolated Converters Mixed-Signal Simulation Flow
- Developed self-checking assertions for Analog Mixed-Signal (AMS) simulations of an isolation ADC, ensuring robust, and automated verification
- Analyzed and enhanced scan coverage to improve test quality and fault detection in an isolated ADC
- Set up a UVM-MS testbench for an isolation ADC with an integrated DC-DC converter:
1. Customized and adapted Python scripts to support the testbench environment
2. Designed and implemented a UVM agent for interfacing with the test protocol
3. Extended the testbench with UVM-MS bridge to enable UVM based mixed-signal verification
4. Developed comprehensive test cases to validate analog and digital functionality - Collaborated with the Tucson, AZ-based design team to support the verification of a delta-sigma ADC:
1. Created and executed functional test cases tailored to system requirements
2. Enhanced the existing testbench and checkers to improve verification efficiency and coverage
Design Verification Engineer (P2)
Rapidsilicon
Lahore
11.2022 - 10.2023
- Led the verification team in developing and executing end-to-end strategies for unit/IP and SoC-level projects, ensuring high-quality deliverables through close collaboration with cross-functional teams including design, firmware, and validation
- Conducted full-fledged verification of a complex SoC integrating reprogrammable logic, memory subsystems, and RISC-V CPUs
- Integrated Synopsys AMBA protocol and LP/DDRx VIPs into a modular UVM testbench for SoC-level verification
- Led bring-up and SoC-level verification of LP/DDRx subsystems, including development of performance monitoring components
- Designed and implemented synchronization mechanisms enabling seamless communication between embedded CPUs and the UVM testbench
- Developed and bound SystemVerilog assertions for time-critical IPs within the SoC testbench to ensure timing and functional correctness
- Applied formal verification techniques for connectivity and protocol compliance using dedicated checkers
Lead Engineer, SoC Verification (P1)
Rapidsilicon
Lahore
12.2021 - 10.2022
- Led design verification efforts for both unit/IP and SoC-level projects, managing team execution and technical deliverables
- Verified complex SoCs integrating reprogrammable logic and a wide range of peripheral/IP components
- Achieved functional and code coverage targets across SoC and IP verification projects, ensuring compliance with quality standards
- Successfully signed off the full verification of the first reprogrammable SoC on TSMC 16nm (FFT) technology
Associate Design Engineer
Lampro Mellon
Lahore
10.2020 - 11.2021
- Developed robust, modular, and reusable UVM Verification IPs (VIPs) for both in-house and third-party IPs
- Led onboarding and seamless integration of VIPs into System-on-Chip (SoC) TB environment
- Built standardized, reusable UVM testbench environments tailored for SoC-level verification
- Drove coverage closure at both IP/unit and SoC levels, ensuring verification completeness and quality
- Designed advanced, synthesizable internal IPs aligned with modern semiconductor design standards
Trainee Design Engineer
Lampro Mellon
Lahore
01.2020 - 10.2020
- Completed a rigorous training program focused on developing core competencies for the semiconductor industry
- Gained proficiency in advanced computer architecture concepts including RISC-V, MIPS, and LC-3
- Acquired hands-on experience with hardware description languages such as Verilog and SystemVerilog for digital design and verification
Education
M.Sc. - Communications And Electronics Engineering
Technical University of Munich (TUM)
Munich, Germany09.2025
B.Sc. - Electrical Engineering
University of Engineering And Technology (UET) Taxila
Taxila, Punjab, Pakistan08.2019
Skills
Technical Skills:
- Digital/AMS Design Verification (IP/SoC)
- Debugging
- eFPGA Verification
- Logic Synthesis
- DFT
- Scan-chain/BIST
- Gate-level Verification
Soft Skills:
- Team Player
- Teamwork
- Team Building
- Excellent Communication and Interpersonal Skills
- Cross-functional coordination
- Ability to learn and adapt quickly
Verification Methodologies:
- UVM/UVM-MS
- Formal Verification
- Assertion based Verification (ABV)
- Constrained-random Verification
- Coverage-driven Verification
- CoCoTB/PyUVM
Programming Languages:
- Verilog / Verilog-A / Verilog-AMS
- SystemVerilog
- OOP
- C/C
- SystemC
- Python
- RISCV/ARM Assembly
Digital/Mixed-signal Modeling:
- Wreal modeling
- SV-RNM modeling
- Verilog-A/Verilog-AMS modeling
Design/Simulation Tools:
- Cadence Xcelium/Simvision
- Cadence Jaspergold
- Cadence Virtuoso/ViVA
- Cadence Spectre
- Cadence Vmanager
- Synopsys VCS/Verdi
- Mentor Graphics Modelsim/Questasim
- MATLAB/Simulink
- LTspice
- Visual Studio Code
Project Management Tools:
- Git
- Github
- Jira
- Confluence
Documentation Tools/Skills:
- Microsoft Word/Excel/Powerpoint/Visio
- LaTeX
Operating Systems:
- Linux
- All MicrosoftTM OS
Awards
Employee of the Year, Rapidsilicon, 2022
Hobbies and Interests
- Reading
- Traveling
- Football (Fussball)
- Cricket
Languages
Urdu
First Language
English
Advanced (C1)
C1
German
Beginner
A1
References
References available upon request.
Timeline
Master Thesis Student
Texas Instruments
04.2025 - 09.2025
Digital Design Engineering Working Student
Texas Instruments
10.2024 - 03.2025
Digital Design Engineering Intern
Texas Instruments
05.2024 - 10.2024
Design Verification Engineer (P2)
Rapidsilicon
11.2022 - 10.2023
Lead Engineer, SoC Verification (P1)
Rapidsilicon
12.2021 - 10.2022
Associate Design Engineer
Lampro Mellon
10.2020 - 11.2021
Trainee Design Engineer
Lampro Mellon
01.2020 - 10.2020
M.Sc. - Communications And Electronics Engineering
Technical University of Munich (TUM)
B.Sc. - Electrical Engineering
University of Engineering And Technology (UET) Taxila
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