Summary
Overview
Work History
Education
Skills
Websites
Timeline
Generic
Evam Gilotra

Evam Gilotra

FPGA Embedded Developer
Bielefeld

Summary

Experienced FPGA Engineer with a proven track record in high-performance digital design, verification, and system integration on AMD/Xilinx Zynq and Virtex UltraScale+ platforms. Specialized in PCIe, DMA, and real-time data acquisition systems, with expertise spanning RTL (Verilog, SystemVerilog, UVM) through embedded Linux integration.

Overview

7
7
years of professional experience
3
3
Languages

Work History

FPGA Embedded Developer

Trenz Electronic GmbH
07.2025 - Current

Design and develop FPGA solutions from RTL to software integration, ensuring seamless functionality analysis and validation of FPGA-based modules.

FPGA System Design

Institute of Data Processing and Electronics(IPE), Karlsruhe Institute of Technology(KIT)
06.2024 - 06.2025
  • Developed a PCIe plugin to control DMA(Direct Memory Access) between FPGA DDR4 and Host system for efficient data transfer.
  • Developed an IP using Verilog and UVM to be used as a L1 trigger(latency ~15μs) for data acquisition for a Qubit Readout System using Zynq RFSoC based Software Defined Radio(SDR) System. The IP has DMA capability with 95% throughput utilization to transfer the data to PS and PL DDR and a python based software driver to control the IP.
  • Cross-compiled an AlmaLinux 8 image for deployment on a Xilinx Zynq UltraScale+, and integrated the IP core along with the corresponding software driver to ensure seamless interaction between the FPGA hardware and the embedded Linux system.

ASIC Design Engineer (Part-time)

Hahn-Schickard
12.2023 - 02.2025
  • Completed RTL Design and Verification of feature extraction module with 17 features for a Decision Tree Classifier ASIC(22nm) using Cadence toolchain.
  • Optimized the feature extraction module for lower power vs accuracy of the classifier and integrated it with the Decision Tree Classifier Module.

FPGA Engineer (Full-time)

Drut Networks India LLP
06.2020 - 10.2022
  • Completed design and verification of FPGA based prototype to enable PCIe Gen3/4 over photonics ensuring ~100ns latency overhead for disaggregated resource infrastructure for GPU, FPGA, SSD, DDR3/4 etc.
  • Extensive use of System Verilog and VHDL for performing functional simulation, debugging, synthesis, timing closure and verification on AMD Zynq and Virtex UltraScale+ in a lab environment.
  • Worked towards regular releases while maintaining source code using Git.
  • Collaborated with Software teams to resolve bugs in the design and worked towards continuous improvement of the datapath.

Bachelor Thesis & Research Internship

Chair for Embedded Systems, Karlsruhe Institute of Technology(KIT)
07.2018 - 06.2019
  • Designed and implemented a hardware accelerator for matrix multiplication (using Verilog and Vivado HLS) to speed up Convolution Neural Network-based Machine Learning algorithms.
  • Design was prototyped on Xilinx Zynq Ultrascale+ and integrated with an existing framework to achieve 140x faster results as compared to A53 Arm processor.

Education

MSc - Embedded Systems Engineering

University of Freiburg
04.2025

Bachelor of Engineering(Hons.) - Electronics and Electrical Engineering

Birla Institute of Technology and Science, Pilani
05.2019

11th to 12th class - undefined

Bal Bharati Public School
Pitampura, Delhi
03.2014

1st to 10th Class - undefined

Bal Bharati Public School
Pitampura, Delhi
03.2012

Skills

  • Programming Languages: System Verilog, Verilog, UVM, C/C, Python, Tcl scripting
  • Development Tools: AMD Vivado, Mentor Graphics(Siemens EDA), Cadence ASIC Development Kit, AMD Vitis, AMD Petalinux, Git, Makefiles, Jira (Proficient at Linux and Windows Environments)
  • FPGAs used: AMD Zynq Ultrascale, AMD Virtex Ultrascale
  • Communication Protocols: PCIe Gen3/4, AXI, DDR3/4, I2C, SPI, Wishbone, Aurora
  • Leadership roles: Sound and Infra Head, Spree’17 at BITS Pilani University
  • Hobbies: Badminton, Cycling, Fiction History books

Timeline

FPGA Embedded Developer

Trenz Electronic GmbH
07.2025 - Current

FPGA System Design

Institute of Data Processing and Electronics(IPE), Karlsruhe Institute of Technology(KIT)
06.2024 - 06.2025

ASIC Design Engineer (Part-time)

Hahn-Schickard
12.2023 - 02.2025

FPGA Engineer (Full-time)

Drut Networks India LLP
06.2020 - 10.2022

Bachelor Thesis & Research Internship

Chair for Embedded Systems, Karlsruhe Institute of Technology(KIT)
07.2018 - 06.2019

Bachelor of Engineering(Hons.) - Electronics and Electrical Engineering

Birla Institute of Technology and Science, Pilani

11th to 12th class - undefined

Bal Bharati Public School

1st to 10th Class - undefined

Bal Bharati Public School

MSc - Embedded Systems Engineering

University of Freiburg
Evam GilotraFPGA Embedded Developer