An innovative Academician with 2.5 years experience on bringing proven success in implementing technology based curriculum delivery and assessment tools. Skilled multitasker with superior work ethic and good teamwork, problem-solving and organizational skills. Willing to take on any task to help team. Reliable and dedicated team player with hardworking and resourceful approach.
Part time job
In the role as a Student Technical Intern at NXP Semiconductors, I assisted in integrating VIP in SystemC and System Verilog virtual prototype models, developed UVM connections, and created unit test cases using the SCML2 library using Synopsys Virtual prototyping, Verdi and VCS tools .
• Assisted in integrating a VIP in both SystemC and System Verilog Virtual
prototype model
• Developed System Verilog UVM and SystemC UVM TLM2 connections
• Created unit test cases using the SCML2 library for functional modeling
Programming
undefinedDiploma in Computer Applications (DCA
Learning UVM testbench with xilinx vivado 2020
Python
The complete UVM system Verilog step by step guide for 2020
Diploma in UNIX and C (DUC)
Diploma in Computer Applications (DCA