Summary
Overview
Work History
Education
Skills
Timeline
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Inna Makyan

Inna Makyan

ASIC Physical Design Engineer
Munich

Summary

With over 7 years of experience in digital design, I have successfully contributed to four tapeouts at Qualcomm and two tapeouts at Apple, consistently delivering designs on time and without issues. I am skilled in executing complex designs and managing the entire process from netlist to GDS, including floor planning, place and route (P&R), and signoff checks. I am motivated, eager to learn, and have always demonstrated strong team-player soft skills. I don’t shy away from challenges, take responsibility for my actions, openly admit my mistakes, and hold myself accountable. Clear communication and problem-solving are key strengths that have enabled me to thrive in high-pressure environments.

Overview

8
8
years of professional experience
4
4
Languages

Work History

Senior ASIC Physical Design Engineer

Apple
06.2022 - Current
  • Executed floor planning (FP) and place and route (P&R) for modem designs with multi-voltage, multi-clock configurations and advanced technology nodes, spanning the entire process from netlist to GDS.
  • Ensured closure and signoff for timing, physical verification (PV), EMIR, LEQ, CLP, and other signoff checks.
  • Participated in innovative experiments to improve design methodologies and workflows.
  • Acted as the primary point of contact for the internal ECO tool, assisting with initial debugging, resolving known issues, collecting recurring problems, and reporting them to the tool development team.
  • Collaborated with internal flow teams to integrate tools and methodologies into designs effectively.
  • Worked on a high-speed, complex design with challenging interface timing requirements.
  • Partnered with cross-functional teams across multiple locations to troubleshoot and resolve design, flow, and tool-related challenges.
  • Mentored and supervised junior engineers and interns, fostering technical growth and teamwork.

Senior ASIC Physical Design Engineer

Qualcomm
01.2019 - 04.2022
  • Executed floor planning (FP) and place and route (P&R) for modem designs with multi-voltage, multi-clock configurations and advanced technology nodes, managing the process from netlist to GDS.
  • Achieved closure for timing, physical verification (PV), EMIR, LEQ, and CLP.
  • Collaborated closely with cross-functional teams across multiple sites to resolve design, flow, and tool-related issues.
  • Supervised and mentored junior engineers and interns.

ASIC Physical Design Engineer

Cisco
03.2017 - 01.2019
  • Performed floor planning, place and route (P&R), and timing closure for memory-dominated designs.
  • Developed a data reporting dashboard and integrated it into the P&R flow using Python, HTML, CSS, and TCL

Digital Design Engineer ( Intern)

Synopsys
07.2016 - 03.2017
  • Responsible for creating DDR PHY analog and digital packages and ensuring the quality of their components.
  • Collaborated closely with project managers and engineers to resolve issues identified during package development and quality assurance.
  • Automated QA and verification processes to improve efficiency.

Education

Master of Science - Integrated Circuits

NPUA ( Synopsys Armenia Education Department)
Yerevan, Armenia
05-2022

Bachelor of Science - Electronic Means

National Politechnic University of Armenia
Yerevan, Armenia
05-2017

Skills

    Digital Design Tools

    Floor Planning & P&R

    Timing Analysis & Signoff

    Scripting Languages

    Team Collaboration

    Continuous Learning & Self-Motivation

    Accountability & Responsibility

Timeline

Senior ASIC Physical Design Engineer

Apple
06.2022 - Current

Senior ASIC Physical Design Engineer

Qualcomm
01.2019 - 04.2022

ASIC Physical Design Engineer

Cisco
03.2017 - 01.2019

Digital Design Engineer ( Intern)

Synopsys
07.2016 - 03.2017

Master of Science - Integrated Circuits

NPUA ( Synopsys Armenia Education Department)

Bachelor of Science - Electronic Means

National Politechnic University of Armenia
Inna MakyanASIC Physical Design Engineer