Summary
Overview
Work History
Education
Skills
Websites
Additional Information
Publications
Timeline
Generic

Muhammad Ali

Dresden

Summary

Interests: Computer Architecture, System Architecture, Hardware Design, RISC-V, FPGA, SoC, MPSoC, Simulations, Machine Learning

Programming Skills: VHDL/Verilog/SystemVerilog, C/C++, SystemC, Xilinx HLS, Python, TCL

Tools: Xilinx Vivado/Vitis, RISC-V GNU toolchain, Synopsys ASIP Designer

Overview

11
11
years of professional experience
6
6
years of post-secondary education
2
2
Languages

Work History

Wissenschaftlicher Mitarbeiter

Barkhausen Institute
Dresden
12.2024 - Current

Current Focus:

  • Research in the field of scalable and trustworthy digital hardware platforms (multiprocessor systems)
  • Ultra small RISC-V for control of Neural Processing Units (NPU)

Wissenschaftlicher Mitarbeiter

Technische Universität Dresden
Dresden
07.2018 - 06.2024

PhD Focus: Methods for Designing and Optimizing Processors for Neural Networks (defense pending)

Focus on

  • RISC-V based SIMD extensions (packed and vector)
    Modular MPSoC for scalability and flexibility
    Simulation and profiling tools for initial evaluation

Research Projects

  • Datenfunknetz mit Adaptivhardware und KI-Optimierung zur Reduktion des Energieverbrauchs (DAKORE) (2022 - 2024)Development of energy-efficient radio access networks using novel power amplifiers and adaptive control algorithms based on AI
    Focus on Packed-SIMD and non-standard extensions for RISC-V processor, and energy-efficient Neural Processing Unit (NPU) on Xilinx FPGA for AI
  • Embedded Artificial Technical Industrial Applications (CORNET-AITIA) (2019 - 2021)Develop "Best practices for embedded AI" on 4 application domains: Embedded Security, Smart Sensors, Industry 4.0, and Automotive and Mobile Robotics
    Focus on RISC-V MPSoC and Vector Extensions of RISC-V for AI applications for Embedded Systems
    Funded by the German Federation of Industrial Research Associations
  • Parallel Implementation-Strategies for Highly Automized Driving (BMBF PARIS) (2018-2020)Design an energy-efficient heterogeneous multiprocessor architecture for self-learning algorithms
    Focus on flexible and modular RISC-V based MPSoC architecture for Xilinx FPGA
    Supported by Bundesministerium für Bildung und Forschung (BMBF)
  • Towards Ubiquitous Low-power Image Processing Platforms TULIPP (2018-2019)Develop a platform of high-performance and energy-efficient image processing for embedded systems
    Focus on low-power techniques e.g. Dynamic Voltage and Frequency Scaling (DVFS) on Xilinx FPGAs
    Fun­ded by the Eu­ropean Com­mis­si­on
  • Conferences & Workshop OrganizationICCAD Workshop 2021 (Cadence Workshop) (Virtual)
    FPL 2021 (Virtual)
    HiPEAC Workshop 2019 (Tullip project booth organization)
  • Academic Support (Labs and Excercises)Hardware Modellierung und Simulation (HMS) - Master's Subject
    Entwurf und Programmierung Eingebetteter Multicore Architekturen (EMCA) - Master's Subject

Reference:

Prof. Dr.-Ing Diana Göhringer

Technische Universität Dresden (TUD),

Chair of Adaptive Dynamic Systems (ADS)

email: diana.goehringer@tudresden.de

Master's Thesis

Robert Bosch GmbH
Renningen
05.2017 - 11.2017

Adaption of RISC-V ISA (Instruction Set Architecture) on Multi Channel Sequencer (MCS).

  • Evaluation and comparison of RISC-V and MCS ISA (Bosch Processor IP)
  • Implementing RISC-V ISA for MCS specification in SystemC
  • Evaluation of RISC-V based MCS architecture

Reference:

Falk Rehm

Bosch Research

Senior Manager & Expert Embedded AI & HW/SW Codesign

email: falk.rehm@de.bosch.com

Assistant Engineer

Inspectest Pvt. Ltd.
Lahore
02.2014 - 12.2014
  • Industrial instrument Calibration and testing.
  • Assign responsibilities to calibration tech/inspectors and prepare execution plan for site and calibration lab.
  • Receive all the incoming calibration jobs. Carry out method validation of calibration procedures and administer all calibration methods as per laid down procedures.

Education

Master of Science - Embedded Systems

Technische Universität Chemnitz
Chemnitz, Germany
04.2015 - 04.2017

Bachelor of Science - Electrical Engineering

National University of Sciences And Technology (NUST-SEECS)
Islamabad, Pakistan
04.2009 - 04.2013

Skills

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Additional Information

German Driving Licence Class B, German Niederlassungserlaubnis

Publications

  • P-CORE: Exploring RISC-V 'P' Packed-SIMD Extension for CNNs, M. Ali et al., Submitted, IEEE Transactions on Computers, 2024
  • Application Specific Instruction-set Processors (ASIPs) for Deep Neural Networks: A Survey, M. Ali et al., Submitted, IEEE ACCESS, 2024
  • A Survey on Reconfigurable Neural Processing Units for Deep Learning, M. Helbig, M. Ali et al., Submitted, IEEE ACCESS, 2024
  • RV-ProViler: Evaluating RISC-V ISA for Application-Specific Requirements, M. Ali et al., NorCAS, 2024
  • RV-VP2: Unlocking the potential of RISC-V Packed-SIMD for Embedded Processing, M. Ali et al., International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation: SAMOS, 2024
  • Unlocking the Potential of RISC-V Heterogeneous MPSoC: A PANACA-based Approach to Simulation and Modeling, J. Haase, M. Ali, & D. Göhringer, International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation: SAMOS, 2023
  • Application Specific Instruction-Set Processors for Machine Learning Applications, M. Ali, & D. Göhringer, International Conference on Field-Programmable Technology: FPT, 2022
  • AITIA: Embedded AI Techniques for Embedded Industrial Applications, M. Brandalero, M. Veleski, H. G. Muñoz Hernandez, M. Ali et al., 31st International Conference on Field-Programmable Logic and Applications: FPL, 2021
  • A Parametrizable High-Level Synthesis Library for Accelerating Neural Networks on FPGAs, L. Kalms, P. Amini Rad, M. Ali et al., Journal of Signal Processing Systems, 2021
  • Power-Aware Computing Systems on FPGAs: A Survey, G. Akgün, M. Ali et al., 31st International Conference on Field-Programmable Logic and Applications: FPL, 2021
  • Vector Processing Unit (VPU): A RISC-V based SIMD Co-processor for Embedded Processing, M. Ali et al., Euromicro Conference on Digital System Design: DSD, 2021
  • AITIA: Embedded AI Techniques for Embedded Industrial Applications, M. Brandalero, M. Ali et al., International Conference on Omni-layer Intelligent Systems: COINS, 2020
  • Domain Adaptive Processor Architectures, F. Fricke, S. Mahmood, J. Hoffmann, M. Ali et al., Kommunikation und Bildverarbeitung in der Automation, 2020
  • RISC-V based MPSoC design exploration for FPGAs: Area, Power and Performance, M. Ali et al., Applied Reconfigurable Computing: ARC, 2020
  • Modular Memory System for RISC-V Based MPSoCs on Xilinx FPGAs, A. Kamaleldin, M. Ali et al., IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip: MCSoC, 2019
  • Low Power Image Processing Applications on FPGAs Using Dynamic Voltage Scaling and Partial Reconfiguration, A. Podlubne, J. Haase, L. Kalms, G Akgün, M. Ali et al., Conference on Design and Architectures for Signal and Image Processing: DASIP, 2018

Timeline

Wissenschaftlicher Mitarbeiter

Barkhausen Institute
12.2024 - Current

Wissenschaftlicher Mitarbeiter

Technische Universität Dresden
07.2018 - 06.2024

Master's Thesis

Robert Bosch GmbH
05.2017 - 11.2017

Master of Science - Embedded Systems

Technische Universität Chemnitz
04.2015 - 04.2017

Assistant Engineer

Inspectest Pvt. Ltd.
02.2014 - 12.2014

Bachelor of Science - Electrical Engineering

National University of Sciences And Technology (NUST-SEECS)
04.2009 - 04.2013
Muhammad Ali