Nandakishor Yadav
Integrated Circuit Design Engineer
Dresden
Summary
Accomplished Integrated Circuit Design Engineer with a proven track record at Fraunhofer Institute, specializing in mixed-signal design. Significantly enhanced AI accelerator designs through innovative engineering solutions and collaborative project execution.
Overview
9
9
years of professional experience
5
5
years of post-secondary education
1
1
Certification
Work History
Integrated Circuit Design Engineer
Fraunhofer Institute for Production Technology
Dresden
2020.09 - Current
- Implemented data converters (ADC and DAC), VCO, Low dropout regulators, voltage references, ferroelectric memory architecture and Sense amplifier design under various conditions.
- Provided key input during project planning, ensuring adequate resources were allocated to IC design team for successful project execution.
- Collaborated with team members to develop high-performance integrated circuits for AI accelerator design.
Senior Research Associate
Ilinois Institute of Technology
Chicago
2019.07 - 2020.09
- Designed Analog and Mixed signal circuits for SRAM based computation in memory design. SRAM bit cell, SRAM architecture , column and row decoder, sense amplifier design
- Supervised Master and Ph.D. students and executed research project with team members
Post Doctoral Fellow
Indian Institute of Technology Indore
Indore
2015.12 - 2018.09
- Conducted in-depth research on SRAM based Computation in memory design, collaborated with colleagues to gather research
Education
Ph.D. - Process Variation And NBTI/PBTI Aware SRAM Design
ABV-Indian Institute of Information Technology
Gwalior, India 2011.01 - 2015.09
M.Tech in Microelectronics - Integrated Circuits And IC Technology
Panjab University Chandigarh
Chandigarh, India 2001.04 -
Master of Science - Electronics
Devi Ahilya University Indore,
Indore, India 2001.04 -
Bachelor of Science - Electronics
Devi Ahilya University Indore
Indore, India 2001.04 -
Skills
Mixed-Signal Design: ADC, DAC, VCO, voltage references, LDO regulator, charge-pump, power supply, sense Amplifier, SRAM and ferroelectric memory bit-cell and array
Digital Circuit Design: Column and row decoder design, serial interface deign
PDK design: Abstract, LEF and timing lib
Cadence Skill and TCL programming
Mixed-signal DRC , PEX and LVS with different vendor IP
Spice modeling (in system verilog)
Certification in Machine learning and deep learning
Adaptability and Teamwork
Languages
English
Bilingual or Proficient (C2)
German
Elementary (A2)
Hindi
Bilingual or Proficient (C2)
Certification
Machine learning and deep learning
EDA tools
Circuit simulation using Spectre/Hspice/MMSIM, layout design, DRC, LVS and RC extraction, Post layout simulation,
RC and latch-up management, well proximity correction, power management. Design Compiler and Cadence Innovus for logic synthesis and PNR respectively
Timeline
Integrated Circuit Design Engineer
Fraunhofer Institute for Production Technology
2020.09 - Current
Senior Research Associate
Ilinois Institute of Technology
2019.07 - 2020.09
Post Doctoral Fellow
Indian Institute of Technology Indore
2015.12 - 2018.09
Ph.D. - Process Variation And NBTI/PBTI Aware SRAM Design
ABV-Indian Institute of Information Technology
2011.01 - 2015.09
M.Tech in Microelectronics - Integrated Circuits And IC Technology
Panjab University Chandigarh
2001.04 -
Master of Science - Electronics
Devi Ahilya University Indore,
2001.04 -
Bachelor of Science - Electronics
Devi Ahilya University Indore
2001.04 -
Machine learning and deep learning
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