Rebecca Grancaric

Working on PMICs that are tailored to the specific customer requirements. Driving customer technical interaction. Managing and coordinating a team to reply in timely manner to customer's RFI/RFP. Defining a new custom power products - modeling, system and design level implementation, floorplan, package selection, area estimations (layout + packaging), BOM (external components), thermal simulation and other necessary work to offer a complete solution. Working on competitor analysis - teardowns, measurements in the lab, reverse engineering and PCB design.

Analyzing the existing portfolio of ICs within sensor solutions across all the product lines (BOM analysis) focusing on Power ICs. Trying to identify similarities, requirements, ways to optimize in terms of all the relevant parameters, both from technical and financial perspective. Providing a technical interface between the R&D and the suppliers. Supporting R&D in the early phase of development with reviewing different sensor schematics, simulating individual IC behavior (LTspice) and selecting strategically right ICs. Working on reference design library to enable efficient re-use of IC implementations (EDA System Xpedition Enterprise).

Architecture definition and concept development to enable next generation power electronics solutions for flagship products. Overseeing the overall IP development cycle. Provide a direct interface to the customer or working with sales department on technical requirements and system performance optimization. Specifying external components and maintenance of product collateral such as product data sheet. Ensuring functional safety by complying with automotive requirements. Working with application engineers in the laboratory to support customers in their application design process.

Design of high-performance DC/DC switching converters for consumer, industrial and automotive applications in Cadence Design environment. Topology definition of Buck schemes. Focus on supply voltages of 0.6V - 6V and delivering output currents up to 4A with fully-integrated solutions operated at switching frequencies in the range of 1MHz - 4MHz. Involvement in the overall design cycle starting with modeling and a feasibility study, proceeding towards transistor-level implementation and finally supervising the layout and supporting post-silicon validation. Analog circuit design using BiCMOS (0.35 µm, 0.18 µm tech Nodes). Close collaboration with project manager, systems, application and product marketing engineers to support product definition and development according to customer requirements. Student coaching.

Organizing technical cross-functional trainings describing the entire product life cycle with the goal being an improvement of communication between different roles, faster integration of newcomers and knowledge sharing.

The topic of my Master's thesis was to improve an existing buck converter in regards of improving the cost, silicon area and circuit performance with simpler solutions. The buck converter was analyzed and redesigned from a simple circuit towards more complicated ones. The blocks included in my thesis were delays, enable buffers, ramp circuit, under voltage lockout, thermal shutdown, power good, error amplifier, gate driver and current sensing. The tool to design this high efficiency synchronous step-down converter operating with an adaptive off-time and peak control scheme was Cadence Virtuoso simulation environment of ADE and ADEXL: Corner and Monte Carlo Simulations.

Theoretical training about Linux and project that they are working on.

At the beginning of the internship I was provided with intensive theoretical training on-chip ESD protection in all important aspects such as strategy, layout and measurements. This in-house training took about two weeks. After that I was included the engineering team and assigned to the ongoing research and development project within Sofics. I assisted in designing different implementations of an ESD/EMC safe LIN driver IC.My task was to design circuit using SPICE simulation software and the actual layout of the driver circuitry itself as well. After the tape-out of the IC mentioned above I continued measuring and analyzing low and high voltage ESD protection devices in a 110nm CMOS process.