Syed Faraz Uddin
Bietigheim-Bissingen,BW
Summary
Organized and dependable candidate successful at managing multiple priorities with a positive attitude. Willingness to take on added responsibilities to meet team goals.
Overview
8
8
years of professional experience
1
1
Certification
Work History
PCB AND PACKAGE LAYOUT ENGINEER IN POWER ELECTRONIC FIELD
HUAWEI Nuremberg R&D Centre
06.2023 - Current
- Responsible for PCB and power package layouts on Zuken PCB design software
- Responsible for building component libraries for layout software
- Responsible for exporting 2D/3D simulation model structures of PCB or packages
- Support of simulation engineers to optimize simulation model
- Support of package experts, process engineers and manufacture engineers for PCB and package manufacture
- Learning Zuken PCB design software and training fellow colleagues as well
- Successfully completed CR-8000 basic compact training from ZUKEN (Certificate of training can be provided upon request).
PCB LAYOUT/IC PACKAGE LAYOUT ENGINEER
iPronics Programmable Photonics
06.2021 - 03.2023
- Design single sided, double sided and multi-layered silicon phtotonic IC based PCB's layout using industry standard techniques, ensuring consideration for DFM/DFT have been made
- Full involvement in launch of MVP
- Working in multi-cultural environment with Engineers from different parts of world working well in team environment
- Responsible for completing Commercial DC PCB layouts in accordance with agreed project time, cost, quality and performance requirements using CADENCE ALLEGRO, ORCAD software for Layout and Schematic Capture
- Creation of 3D model of PCB layouts and get it verified from Mechanical Engineer
- Designing fine pitch Substrate layout designs/IC Package/Flip Chip layout MCM (Multi-chip module) of Photonic Integrated Circuits on APD (Allegro Package Designer) i.e IC Package designing of BGA
- Worked on Substrate designs with LID, thermistors and Fiber Array
- Understanding of thermal and mechanical aspects of PCB's and Substrates
- Designing Wirebonding PCB and Motherboard PCB's with LGA/BGA/Molex connectors
- Responsible for conducting meeting with Cadence Team and getting training of softwares and effective use of PCB design/IC Package design
- Working with Mechanical/Packaging/Validation/Photonics department to ensure that electronics part of product is working well and there is no issues in it
- Working in collaboration with Photonic Integrated Design Manager for development of next generation Photonic Chip
- I.e Reduction in cost of photonic chip fabrication, To optimize chip pattern/bump pads co-ordinates of photonic chip for better performance and better signal Intergity
- Responsible for converting PCB layouts done in different softwares (KICAD, ALTIUM etc) into CADENCE format (Schematic and layout)
- Responsible for designing footprint and schematic symbols of resistors, capacitors, inductors etc
- Experience in creating draft schematics
- Responsible for maintaining technical documentation for all PCB designs and IC Package Designs
- Maintaining technical documentation of UL94 -V0 and ROHS compliance certification of each PCB projects
- Writing down minutes of meeting after every technical meeting/discussion via call with customers, suppliers etc
- Strong knowledge of LGA, BGA attachment, design techniques
- Responsible for generating Gerber/Assembly package for manufacturing and assembly of PCB's
- Responsible for communicating with PCB manufacturers/assemblers on post gerber release manufacturing issues
- Understanding and implementing correct Interfacing, Assembly of PCB/IC Packaging Projects
- Training junior engineers on Cadence ORCAD and Allegro PCB Editor software
- communicating with PCB, Substrate manufacturers within Europe and outside Europe as well.
PCB LAYOUT ENGINEER/IC PACKAGE LAYOUT ENGINEER
R&D ALTANOVA-Advantest Group
02.2016 - 06.2021
- Design single sided, double sided and multi-layered PCB layouts using industry standard techniques, ensuring consideration for DFM/DFT have been made
- Responsible for completing ATE PCB layout designs in accordance with agreed project time, cost, quality and performance requirements using CADENCE ALLEGRO, ORCAD software for Layout and Schematics
- Designing fine pitch Substrate designs/IC Package/Flip Chip designs MCM (Multi-chip module) for customers like SV-PROBE, AMD, INTEL, FORM FACTOR, TERADYNE, MEDIATEK on APD (Allegro Package Designer) i.e IC Package designing of BGA
- Implementing constraints (DRC) in Cadence Allegro Package Designer for designing of RDL and CORE layers
- Using RDL layers for transition of signal, power and GND
- Take appropriate steps to make sure enough clearance of copper-copper in layout
- Using Micro/Core vias for transition from C4 level to BGA level
- Taking care of co-planarity and stability in substrate designs
- Schematic capture, library management, footprint and symbol creation
- Performing design constraint requirements (i.e
- Differential Routing, Controlled Lengths/Delay, Crosstalk Control, etc.) in critical boards
- Schematic capture, circuit placement/routing and documentation of board layout
- In-depth knowledge of design concepts and safety standards of PCB
- Good understanding and practical knowledge of blind, buried, micro vias concept
- Working on high density BGA pin count devices
- Knowledge and practical experience on EMC, grounding, crosstalk, signal integrity, impedance control
- Proven experience on PCB layout of power boards, i.e low voltage/low current PCB design, power supplies, isolation, clearance, creepage, etc
- Understanding and application of DFx (DFM, DFA and DFT)
- Hands on experience in designing layout of ATE Final Test/Probe Card boards of MEDIATEK, AQUANTIA SEMICONDUCTORS of more than 35 layers board
- Working on DUT (Device under test) pitch up to 0.5mm
- Working on ATE/testing boards/Functional test PCB of HI-SILICON, AQUANTIA, JUNIPER NETWORKS, NXP Semi-conductors, INTEL, MELLANOX and RF boards of BROADCOM
- Working on high speed signals/routing of XILINX, AMD, and NXP boards
- Worked on SERDES high speed loopback signals
- Completed overall PCB projects of AQUANTIA, NXP, NVIDIA, MEDIATEK and XILINX including component development, ORCAD schematic design, layout designing and NETLIST/NETLENGTH excel reports
- Extensive knowledge in and designed ATE boards on Advantest 93K, T2K, Ultra Flex and J750 (E320) tester configurations
- Communicating with Application Engineers based in San Jose, Costa Rica, Canada, Florida, Taiwan and Shanghai
- Worked on Phase matching, Resistance matching of non-impedance/impedance controlled signals
- Working well in team environment with design engineers, test engineers, QA Engineers and software engineers
- Oversee fabrication and testing of systems after installation to ensure performance and client requirements are meet
- Understanding and implementing correct Interfacing, Assembly of PCB/IC Packaging Projects
- Working with Component Engineers/Application Engineers regarding creation of Bill of Materials
- Create and apply design and development standards and procedures
- Good knowledge of Fabrication and assembly drawings
- Creation of DXF and PDF files for assembly purposes
- Planning cost reduction strategies in coordination with PCB design staff
- Communicating with Signal/Power Integrity Engineers
- Good understanding & knowledge of engineering drawings
- Gerber Generation, ODB++ generation and checking using CAM350.
Education
Bachelor of Science in Electronics Engineering (B.S) - Electronic Engineering
Sir Syed University of Engineering & Technology
Karachi ,pakistan03.2015
Skills
- Analytical thinking
- Strong email communication skills
- Effective Communication skills
- Zuken CR-8000
- ORCAD
- Cadence Allegro PCB Editor
- Cadence Allegro Package Designer
- Saturn PCB Design Toolkit
- FreeCAD
- AutoCAD
- Analytical and Critical Thinking
- Design for Manufacturability
Note
Notice Period : 3 month
Personal Information
Title: Pcb Layout/IC Package Layout Engineer
Hobbies and Interests
Cricket
Certification
Zuken Compact CR-8000 training - July 2023
Given by Zuken GmbH
Languages
English
Advanced (C1)
Urdu
Bilingual or Proficient (C2)
German
Beginner (A1)
Timeline
PCB AND PACKAGE LAYOUT ENGINEER IN POWER ELECTRONIC FIELD
HUAWEI Nuremberg R&D Centre
06.2023 - Current
PCB LAYOUT/IC PACKAGE LAYOUT ENGINEER
iPronics Programmable Photonics
06.2021 - 03.2023
PCB LAYOUT ENGINEER/IC PACKAGE LAYOUT ENGINEER
R&D ALTANOVA-Advantest Group
02.2016 - 06.2021
Bachelor of Science in Electronics Engineering (B.S) - Electronic Engineering
Sir Syed University of Engineering & Technology
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