Motivated student currently working towards degree in Digital Design and Verification. Skilled in both software programming language Python and hardware description language Verilog, VHDL. Ability to handle projects regarding processor design and test, RTL simulation, deep learning algorithms, Linux OS.
Contributed to research on Transformer-based Base-Caller Design, aimed at locating gene clusters and reading gene sequences from fluorescent images. Achieved cluster quality (Q30: 88 % better ), throughput (16.5% better), and with similar and low error rate (down to 0.137% on average), compared with traditional method.
Contributed Spearhead research on Event-based Visual Odometry Design to obtain trajectory and motion information by processing and analyzing datastreams from event camera. Achieved a significant improvement by reducing translation and rotation errors by 57.44% and 75.95%, respectively, compared to previous work.