Kyung Wook Park

Application Engineering on Calibre Design Solutions, delivering a complete IC verification and DFM optimization EDA platform that speeds designs from creation to manufacturing, addressing all sign-off requirements.

Enhanced end-user experience by incorporating feedback into application design and functionality improvements in nanometer silicon chip Design Frontend area and Manufacturing Backend OPC/RET world. GlobalFoundries, Intel, Infineon, TSMC and STmicro.

Improved application performance by identifying and resolving bottlenecks in customers software systems.

Actively participated in code reviews, debugging, promoting best practices and improving overall code quality across the team.

New job orientation, German language course at CBZ (full-time, further education).

Establishment of own company to export automobile parts.

Distributor to develop European customers, interface roles in automotive parts industries.

Consul Sale Engineer to develop automotive ADAS,

Responsible for Asia sales (China, Korea and Singapore), Digital Signal Processor with multi-cameras. new customer development, Surround-view, Traffic sign recognition technologies.

Writing chip packaging design rules for wire-bond BGA, TSSOP, L-/T-/MQFP. Leadframe, Bonding diagram, redefining and releasing package DRC(Design Rule Check), creating test cases and qualifying package design.

Inteface between chip pacakge product services and backend subcontracts Amkor and ASE.

Securing existing business and successful annual price negotiations.
Close cooperation with marketing, design, products, QA, logistics and Finance teams.
Market and competition analysis, regular reporting on sales activities.

Sales manager working with distributors and regional sales, including ASIC development. Sales representative between HQ and Asia Pacific.
Provide technical supports to customers during development, finalize contracts (NDA, BPA and MOU).

New job orientation due to insolvency of Qimonda(Infineon spin-off).

Took a German course.

Expert in physical design for memory, analog mixed signal layout design.

Provides methods for automation of chip design.

Speaker and leader of a group of worldwide experts in analog design.

Collaborate with CAD and circuit design teams to meet project schedules on time.

Development of innovative design solutions for challenging technical problems, resulting in improved product performance.

Partial revision for 256Mb Low Power SDRAM, setup of design automation with Synopsys' Hercules Physical Verification Suite.

Complete full-chip circuit simulation including core and peripherals for SDRAM and DDR1.
Design of analog and mixed-signal design components, static timing analysis, failure analysis.
Circuit design for power-up, charge pump, regulator, internal power supply, data in/out buffer, state machine.

Floorplan at chip level, architecture, complete chip verification,
Management of design automation flows using Cadence Skills programming language.
P&R (placement and routing) with Synopsys IC Compiler.
Leading TFT company developing standardized designs and processes after merger with LG Semiconductor.
OPC (Optical Proximity Correction) to improve wafer yield. Tape-out for manufacturing.
Strong experience in physical chip design for core and peripheral areas.
Author for DRC and LVS rules using Synopsys Hercules Suite, Cadence Virtuoso and Mentor Calibre.